The present invention relates to an architecture for switching data between individual input and destination resources. More specifically, a bus topology is described herein by which individual data switch modules may be interconnected to provide greater speed, efficiency, and data bandwidth than currently available bus architectures.
Data switch modules which interconnect and switch data between a plurality of input/destination resources, e.g., computer terminals, represent a rapidly developing area of technology. One technique currently employed to implement such data switch modules is known as asynchronous transfer mode (ATM) switching. A building block in an ATM system is a structure known as an ATM switch element. An ATM switch element provides data cell signal routing from one of a plurality of input ports to one or more of a plurality of output ports by maintaining an array of crosspoints for connecting any input port to any output port. ATM switch elements may be aggregated in various patterns to provide an arbitrarily large array of possible interconnections of input ports to output ports, each via a unique path. Such an aggregation of switch elements is typically the basis of a switch module and will be referred to herein generically as an ATM switch.
It is also well known that commercially available switch modules, which have a limited fan-out, may be connected together to increase the number of input/destination resources which may be connected. Various bus configurations have provided varying levels of switching performance. FIG. 1 is a block diagram of a typical ATM bus architecture 10 designed according to the prior art. The system shown includes a plurality of ATM switch modules 12 interconnected via unidirectional data bus links 14, and a header bus 18 at each end. Each switch module 12 is connected to some number of input/destination resources such as, for example, computer terminals, for which the switch module 12 provides data switching. Header buses 18 regulate the flow of data in the system.
Problems associated with the bus architecture of FIG. 1 arise when data must be transmitted between two switch modules which are separated by several intervening switch modules. For example, referring again to FIG. 1, if a resource connected to switch module 12-1 communicates with a resource connected to switch module 12-n, data must be transmitted from module 12-1 and pass through modules 12-2 through 12-(n-1) before arriving at module 12-n. As the number of switch modules, n, increases, this method of transmission becomes increasingly less desirable. Not only is the transmission through every switch module time consuming, it also ties up resources thereby consuming precious data bandwidth.
A bus topology for interconnecting data switching modules (such as ATM switch modules) which addresses these concerns is therefore desirable.